1. Field
This disclosure relates generally to codeword error injection and, more specifically, to codeword error injection via checkbit modification.
2. Related Art
In general, memory units that are protected by error correcting code (ECC) have generated and checked additional error parity information (that is local to the memory units) to detect and correct errors in data stored in the memory units. In contrast, end-to-end ECC (e2eECC) performs error protection code generation at a data generation source, sends data and error protection codes (i.e., a codeword) to intermediate storage when a memory write is initiated by a bus master, and performs an integrity check of the codeword using the previously stored error protection codes at a data sink when a read of the stored data is requested.
In various implementations, error protection codes are generated based on additional information that is associated with data in a storage location in order to protect the data. For example, utilizing address information in the formation of a codeword provides additional error detection capabilities. In general, a codeword includes a set of data bits (i.e., a data field) and a set of ECC checkbits (i.e., a checkbit field). The ECC checkbits are generated based on the content of the data field and address information associated with a location in storage of the codeword. Injecting errors into a transmitted codeword has been desirable to facilitate on-line testing of ECC logic of an integrated circuit (e.g., ECC logic of a system on a chip (SoC)). Error injection has typically been accomplished by dedicated hardware that inverts one or more bits of a codeword. Error injection for e2eECC is more complicated than error injection for ECC as an address component is also included in codeword generation.
Unfortunately, conventional error injection logic, which has been located in a critical timing path (to inject errors in an address), has lengthened the critical timing path. In general, error injection has conventionally required error injection logic to be capable of inverting each individual data bit and checkbit of a codeword, as well as address inputs to checkbit generation logic. In addition, specifying codeword bit(s) or address inputs to be inverted (to facilitate error injection) has required multiple registers and relatively expensive decoders to facilitate injection of desired error patterns. For example, in a system that employs eight checkbits, sixty-four data bits, and twenty-nine address bits, one-hundred one total input bits have required one-hundred one exclusive OR (XOR) gates at each bus master to facilitate error injection into one or more selected information bits.